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RM0008
Advanced-control timers (TIM1&TIM8)
Figure 52. Counter timing diagram with prescaler division change from 1 to 2
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
F7
F8 F9 FA FB F C
00
01
02
03
Update event (UEV)
Prescaler control register
0
1
Write a new value in TIMx_PSC
Prescaler buffer
0
1
Prescaler counter
0
0
1
0
1
0
1
0
1
Figure 53. Counter timing diagram with prescaler division change from 1 to 4
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
F7
F8 F9 FA FB F C
00
01
Update event (UEV)
Prescaler control register
0
3
Write a new value in TIMx_PSC
Prescaler buffer
0
3
Prescaler counter
0
0
1
2
3
0
1
2
3
13.3.2
Counter modes
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is
repeated for the number of times programmed in the repetition counter register
(TIMx_RCR). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
Doc ID 13902 Rev 9
257/995
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